In the course of a memory access by a microprocessor, two steps occur. First, an effective address is generated by the program code, and then this address is translated to the real or physical address of a location in memory. Effective address generation most often involves the addition of two operands. In a 64-bit machine, for example, two 64-bit numbers are added to generate a 64-bit effective address. Because translation of the effective address to a real address can take several machine cycles, various caching structures such as the Segment Lookaside Buffer ("SLB") and Translation Lookaside Buffer ("TLB") are employed to speed up the translation process. To assist translation, many of these structures to assist translation rely on a content-addressable memory ("CAM") to store an association between all or part of the effective address and a datum or real address that would be produced in translation.
The current practice of generating an effective address and using this to access a CAM is illustrated in FIG. 2. N-bit adder 201 receives operands A and B, which are added by adder 201 to produce a result A+B, which is then supplied to CAM 200. The matching cells portion of CAM 200 determines whether or not there is an entry K equal to N. If so, then entry K is used within the associated data portion of CAM 200 to output a corresponding real address M.
One problem with the prior art process for producing a real address using CAM 200 is that adder 201 requires a significant amount of cycle time in order to produce the sum resulting in an unacceptable latency factor during a memory access process. As a result, there is a need in the art for an improved process for translating effective addresses into real addresses.